Advances in semiconductor processing technology have made it possible to compact the feature sizes of integrated circuits to allow more transistors to be fabricated on a single semiconductor substrate. For example, the most sophisticated microprocessors being manufactured today typically comprise a single integrated circuit (IC) made up of several million transistors. Although these astounding technological advances have made it possible to dramatically increase the performance and data handling capabilities of today's modern computer systems, these advances have come at the cost of increased power consumption. Increased power consumption, of course, means that there is more heat that must be dissipated from the IC.
Because excessive power consumption and heat dissipation is now a critical problem facing computer designers, various power-saving techniques have evolved for minimizing power supply current levels within computer systems. Many of these techniques adopt the strategy of powering down the microprocessor when not in use to conserve power. This approach, however, is not without drawbacks.
By way of example, a problem arises in multiprocessor (MP) computer systems which employ two or more processors that cooperate to complete system tasks. If one microprocessor has been powered-down (e.g., because its current tasks have been completed or it is otherwise inactive) another microprocessor in the system may continue to perform data transactions on the system bus. The problem is that some the bus transactions may attempt to read/write data stored in a modified state in a powered-down or otherwise inactive microprocessor. Unless there exists some mechanism for monitoring bus activity and updating shared memory locations, data coherency will be lost. Therefore, MP computer systems have a need for a mechanism which makes inactive processors both aware and responsive to bus activity that may attempt to access stale data.
As will be seen, the present invention provides a multiprocessing computer system in which individual processors monitor bus traffic to maintain cache coherency while operating in a reduced power mode. In accordance with the present invention, an inactive or powered-down processor responds to certain bus transactions by writing back modified data to the system bus in a reduced power mode of operation. In addition, the invention functions without latency or intervention from the operating system. Thus, the invention provides a totally transparent way of interacting with an external bus while minimizing power consumption.